About
Full Understanding of the Digital IC Design Flow and the Entire Transformation Process of Taking the Design from RTL to final bitstream on FPGA and GDSII on ASIC. The course includes hands on training on FPGA, and final project Tapeout and fabrication on SKY130. Digital design flow is a lengthy process that involves many steps to take the design from RTL to a working silicon. The objective of this course is to demystify this field and provide in-depth understanding of the different transformations in each design step, how these transformations can affect the final performance metrics, and how to tune the process to meet design specs. Specifically, this course focuses on fundamental elements in the design process, including HDL modeling, event driven simulation, synthesis, timing analysis, technology files, standard cell views, physical design, signoff checks, and test planning. Throughout the course, attendees learn the salient differences in these elements when using FPGA and ASIC platforms.